1. Technical Field
The present invention relates in general to an automatic compensation circuit for "no margin input data" and a clock capable of recognizing the input data normally, in the case that the clock and the data do not have any margin when reading the first data with a clock, and in case that data is inputted without any synchronized clock during designing Application Specific Integrated Circuit (ASIC) or Programmable Gate Array (PGA).
2. Background
Generally, a margin between a clock and input data is a time difference between the clock and the data edge. The margin between the clock and the data is required to read the input data exactly.
If input data has an incorrect location for synchronizing with a clock, and in particular has no margin with respect to the clock (hereinafter, referred to as "no margin input data") when the input data is read, it is required to read the data after matching the data to the clock automatically.
Particularly, the margin between the data and the clock is quite important in an express data processing system (such as, DS-3), and it is required to synchronize the data having no connection with the margin.
When reading input data first for internal logic routing, like for a conventional PGA, a user should check the margin and determine phases between the input data and the clock with the oscillator. And in the case of no margin input data, the user reads the data with the positive or trailing edge where the margin exists.
But, whenever routing an internal logic circuit of a PGA, the circuit routing logic path is different. That is why it is difficult to read the data with the positive or trailing edge after determining the phase of the difference between the data and the clock which is changed.